In a receiving circuit of an LSI (large-scale integrated circuit) for high speed communication, supporting the high-speed serial transfer with a transfer rate in a Giga-bit range, there is provided a serial-to-parallel conversion circuit adapted for converting serially transmitted received data into byte-based parallel data (termed a demultiplexer or DEMUX). This serial-to-parallel conversion circuit includes a code detection circuit for detecting a header byte code for byte alignment (termed a COMMA code) from serially entered received data (see Patent Document 1 below). FIG. 11 hereof shows FIG. 6 of this Patent Document 1 for reference sake. Referring to this FIG. 11, a code detection circuit CDDT of the serial-to-parallel conversion circuit includes flipflops FF60 to FF69, forming a shift register for serial-to-parallel conversion of serially entered received data SDR, NAND gates NA10, NA11, for receiving a preset combination of non-inverting and inverting output signals of the flipflops, and a NOR gate NO1 for receiving output signals of the NAND gates. As for the outputs of the NAND gates NA10, NA11, when the consecutive 10 bits of the received serial data SDR are found to be coincident with the comma code (e.g. the logic signal “0011111010”, the code detection signal COMD goes high at the second next clock cycle as counted from the clock cycle in which the 10 bits of the received serial data are logic data of “0011111010” and, responsive thereto, parallel transfer of the received serial data commences. The Patent Publication 1 discloses a code detection circuit comprising an alternate serial interconnection of plural flipflops and plural 2-input logic gates, in which the flipflops are in operation responsive to received clocks so that output signals of the flipflops are selectively at an effective level when preset directly previous bits of input data serially entered in timed relation to the clocks are coincident with corresponding bits of a check code (comma code), and in which the logic gates discriminate that leading preset bits of input data are coincident with the corresponding bits of the check code or that the output signals of the directly previous flipflop or the next following flipflop are of the effective level and e.g. the next one bit of the input data coincides with the corresponding bit of the check code to transmit the state to the next downstream side flip-flops.
[Patent Document 1]
    Japanese Patent Kokai Publication No. JP-A-11-187002 (pages 2 and 3 and FIG. 6)